1. Field of the Invention
This invention pertains to a switching system which provides communication between a plurality of ports, and more particularly to a system having a common bus over which signals are exchanged between said ports by a time division multiplexing technique.
2. Description of the Prior Art
Various switching networks have been proposed for high speed switching of digital and/or analog signals between a plurality of lines. As the number of lines connected to each network and data transmission increased these networks became more and more complex. Moreover as the amount of information being processed approaches the maximum capacity of a particular network, internal blocking also became frequent. The following United States Patents disclose some of these problems and suggest various solutions thereto.
U.S. Pat. No. 3,694,580 to Inose et al discloses a typical switching system in which two time division multiplexed buses are used as a data transfer means. The PCM signals on the buses are partitioned into frames, each frame comprising a plurality of channels of 8 bit intervals. The bit intervals are further subdivided into minibit intervals. The information contained in these minibit intervals are individually transferred from one bus to another by a complicated scheme in which the contents of some of the minibits of a particular frame are exchanged by delaying them to avoid blocking. A memory is used to keep track of the bits.
U.S. Pat. No. 3,740,483 to Pedersen also pertains to a switching network in which various time slots in a given frame are interchanged as the frame propagates from one stage of the network to the next. As a particular bit stream progresses from line A to line B it may be subject to both space switching and time switching. However, in full duplex communication a corresponding bit stream also progresses from B to A. Since the two paths are complementary, Pedersen eliminates some redundancy by using a bilateral time slot exchanger and a control memory having a single control word to control the interchange of the bit streams in either direction between any two lines.
U.S. Pat. No. 3,787,631 to Lewis discloses a system comprising a plurality of stations interconnected by a control time division switching network. At the beginning of each transmission each station requests a time slot from the control network. The central network detects the first idle time slot in the frame and assigns it to the requesting station. Each station actually takes the time slot following the designated time slot to compensate for various computational delays of the central network.
U.S. Pat. No. 3,920,916 to Brightman et al discloses a digital switching network interconnecting a large number of send and receive circuits by time division multiplexing. Send and receive memory means are used for temporarily storing the data while a proper time slot is assigned to each send/receive pair by a control circuit. The send memory means can transmit data in any sequence ordered by the control circuit. Furthermore a special duplex circuit is provided for two-way communication between a particular circuit pair.